almost 4 years ago

## GSoC #-1: Work Product Summary

This is a summary of the Google Summer of Code project MyHDL: Fixed-point Compiler.

## Code

The entire code can be found in the mep-111 branch of my repository. It has been contained in a single pull request #228 and not yet merged.

The main repository of MyHDL has created a gsoc branch for GSoC projects this year. However, none of the code has been merged in until now.

## Summary of Goals

The goals have been described simply in my proposal:

When the project finishes, MyHDL should have a complete implementation of fixbv and its compiler backend with complete documentation, include tutorials and reference.

It contains 3 parts: front-end, back-end, and documentation. To simply speaking, it is far from saying that the project has been "completed". Although the front-end has been finished, the back-end is still not working, and although I have written many blog posts about my work and the implementation of MyHDL, the documentation of fixbv interface at this time temporarily is still MEP-111.

Here is a detailed description of each part.

### Front-end

Before my project, cfelton has implemented a simple fixbv front-end. It only supports some simple functions. So I made the following improvements:

1. Added support for Python 3.x.
2. Added support for point alignment.
3. Added support for round modes and overflow modes.
4. Added more tests for fixbv front-end in test_fixbv.py.

These improvements made an almost complete change on the previous fixbv implementation, and also affected some other critical code, such as _Signal.py, etc.

It has only some minor issues left now. Because those issues do not affect the core function of fixbv, the implementation of these issues has been put in a lower priority after discussion with mentors.

1. There are still some minor issues marked as @todo after cleaned up cfelton's code.
2. Implementation of fxsum which is described in a previous post. Since it only affects intermediate results, it seems not necessary.
3. Interoperability with intbv. Since intbv could be treated as a fixbv without a fractional part, it is possible to operate between intbv and fixbv. It has been given a low priority since it is not defined in MEP-111 and not so emergent at this time.

### Back-end

At this time, only the tests of Verilog conversion has been implemented. There are a few patches on the back-end code but it is still not working even with those simple test cases.

There are still something that needs to go:

1. Patch AST node visitors for conversion.
2. Patch other parts of the back-end code in order to implement all the functions of fixbv.
3. Make bigger test cases to better check the implementation, such as CORDIC.

### Documentation

Until now, the main documentation of fixbv is MEP-111 of MyHDL project, which is written by cfelton.

I have written some blog posts of some features and issues of fixbv. However, this part has not been merged into a larger documentation. It will be helpful in the future.

## Reasons of Incomplete

1. The plan is too ambitious. I thought it was just a new type on this existing platform. However, I should also review many other parts of work according to different issues that may take.
2. Too much hanging around in the ad hoc issues. While implementing the front-end, there were so many small issues and I have to take time to fix them.
3. Not enough work time. GSoC needs 40 hours per week to work for the project. However, I am in a university located in Japan, and I have to deal with final exams in June and August for spring and summer quarter respectively. It took me a lot of time. I have suggested future GSoC to consider students' time in different regions.

## Future Plan

1. Fully implement the back-end with tests.
2. Merge the documentation to some places like The MyHDL Manual.
3. Implement interoperability between intbv and fixbv.

I have deeply involved in the society of MyHDL. I will contribute to it in the future.